library ieee;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
use ieee.std_logic_1164.all;


entity tb_alu is
end tb_alu;

architecture testbench_arch of tb_alu is
  component alu
    port (opcode         : in  std_logic_vector (2 downto 0);
          A, B           : in  std_logic_vector (31 downto 0);
          output         : out std_logic_vector (31 downto 0);
          negative       : out std_logic;
          overflow, zero : out std_logic);
  end component;

  signal A, B, alu_out             : std_logic_vector (31 downto 0);
  signal opcode                   : std_logic_vector (2 downto 0);
  signal negative, zero, overflow : std_logic;

  constant v1 : std_logic_vector := "00000000000000000000000000000001";
  constant v2 : std_logic_vector := "00000000000000000001001001110001";
  constant v3 : std_logic_vector := "00000000000000000110001000011111";
  constant v4 : std_logic_vector := "00000000000000000110001000011111";
  constant v5 : std_logic_vector := "00000000000000000000000000000000";
  constant v6 : std_logic_vector := "11111111111111111111111111111111";
  constant v7 : std_logic_vector := "10000000000000000000000000000000";
  constant v8 : std_logic_vector := "10000000000000000000000000000000"; 

  procedure println(output_string : in string) is
    variable lout : line;
  begin
    WRITE(lout, output_string);
    WRITELINE(OUTPUT, lout);
  end println;

  procedure printlv(output_bv : in std_logic_vector) is
    variable lout : line;
  begin
    WRITE(lout, output_bv);
    WRITELINE(OUTPUT, lout);
  end printlv;


begin
  DUT : alu
    port map (
      A        => A,
      B        => B,
      opcode   => opcode,
      output   => alu_out,
      negative => negative,
      zero     => zero,
      overflow => overflow
      );


  process

  begin

    println("");
    println("Starting Test");
    assert(1 = 0);
    A <= v2;
    B <= v1;

    wait for 50 ns;

    opcode <= "000";

    wait for 50 ns;

    opcode <= "001";

    wait for 50 ns;

    opcode <= "010";    

    wait for 50 ns;

    opcode <= "011";

    wait for 50 ns;

    opcode <= "100";

    wait for 50 ns;

    opcode <= "101";

    wait for 50 ns;

    opcode <= "110";

    wait for 50 ns;

    opcode <= "111";

    wait for 50 ns;
    assert(1 = 0);
    A <= v4;
    B <= v3;

    wait for 50 ns;

    opcode <= "000";

    wait for 50 ns;

    opcode <= "001";

    wait for 50 ns;

    opcode <= "010";    

    wait for 50 ns;

    opcode <= "011";

    wait for 50 ns;

    opcode <= "100";

    wait for 50 ns;

    opcode <= "101";

    wait for 50 ns;

    opcode <= "110";

    wait for 50 ns;

    opcode <= "111";

    wait for 50 ns;    
    assert(1 = 0);
    A <= v5;
    B <= v6;

    wait for 50 ns;

    opcode <= "000";

    wait for 50 ns;

    opcode <= "001";

    wait for 50 ns;

    opcode <= "010";    

    wait for 50 ns;

    opcode <= "011";

    wait for 50 ns;

    opcode <= "100";

    wait for 50 ns;

    opcode <= "101";

    wait for 50 ns;

    opcode <= "110";

    wait for 50 ns;

    opcode <= "111";

    wait for 50 ns;
    
    assert(1 = 0);
    
    A <= v8;
    B <= v7;

    wait for 50 ns;

    opcode <= "000";

    wait for 50 ns;

    opcode <= "001";

    wait for 50 ns;

    opcode <= "010";    

    wait for 50 ns;

    opcode <= "011";

    wait for 50 ns;

    opcode <= "100";

    wait for 50 ns;

    opcode <= "101";

    wait for 50 ns;

    opcode <= "110";

    wait for 50 ns;

    opcode <= "111";

    wait for 50 ns; 
    

                                                                      

              

    println("Test Complete");
    println("");

    -- end simulation
    wait;

  end process;
end testbench_arch;


